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Espressif Systems /ESP32-S3 /MCPWM0 /CAP_TIMER_CFG

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Interpret as CAP_TIMER_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CAP_TIMER_EN)CAP_TIMER_EN 0 (CAP_SYNCI_EN)CAP_SYNCI_EN 0CAP_SYNCI_SEL 0 (CAP_SYNC_SW)CAP_SYNC_SW

Description

Configure capture timer

Fields

CAP_TIMER_EN

When set, capture timer incrementing under APB_clk is enabled.
CAP_SYNCI_EN

When set, capture timer sync is enabled.
CAP_SYNCI_SEL

capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix
CAP_SYNC_SW

Write 1 will force a capture timer sync, capture timer is loaded with value in phase register.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data